The present invention relates to a method for fabricating a CMOS (Complementary Metal Oxide Semiconductor) field effect transistor with LDD (lightly doped drain) and structure thereof.
The channel length of a MOS field effect transistor (herein referred to as MOS transistor) has been continuously shortened so as to achieve a more highly integrated semiconductor circuit. As a result the electric field tends to be concentrated in the drain, so as to generate hot carriers, which are introduced into the gate. Thus they causes, so-called hot carrier effect, the undesired effect that the hot carriers make the threshold voltage of the transistor unstable, etc.
In order to obviate the hot carrier effect, an insulated spacer is formed on the side walls of the gate by reactive ion etching, so as to obtain a lightly doped drain (LDD) by implanting the same conduction impurity as that of the source and drain into the source and drain in the semiconductor at low concentration.
Referring to FIG. 1, is illustrated a conventional CMOS transistor comprising a PMOS transistor and NMOS transistor formed in one and the same semiconductor substrate.
There are adjacently formed a p-well 4 and n-well 6 on an n-type or p-type semiconductor substrate 2. The p-well 4 and n-well 6 are electrically isolated from each other by a field oxide layer 8. A first source and drain 18, 19 of low concentration are separated by a channel region in the p-well 4. A second source and drain 20, 21 of high concentration are separated with a more distance than the distance between the first source and drain. Over the channel region is formed a gate insulated layer 10, on which is there formed a first gate 12. An oxide layer spacer 16 with a first width is formed on both side walls of the gate 12.
On the other hand, a source and drain 22, 23 are separated by a channel region in the n-well 6. Over the channel region is formed a gate insulated layer 10, on which is there formed a second gate 14. An oxide layer spacer 16 of the first width is formed on both side walls of the gate 14.
The LDD structure such as formed in the well 4 is achieved by a method comprising the steps of forming the first source and drain regions by performing first ion-implantation to the whole surface of a substrate having a gate pattern, and of forming the second source and drain regions of high concentration by performing second ion-implantation to the whole surface of the substrate after forming a spacer on both side walls of the gate.
However, in such a PMOS transistor formed in the n-well, it is difficult to distinguish the low concentration ion-implanted region and high concentration ion-implanted region from each other because of very large out-diffusion of the ion-implanted p-type impurity. Namely, if the ion-implantation for obtaining a high concentration diffusion region is performed after simultaneously forming the spacers of the NMOS and PMOS transistors, the p-type impurity becomes diffused to a distance corresponding to about the width of the spacer, thereby resulting in a single drain (SD) structure.
Referring to FIG. 2, is illustrated another conventional semiconductor transistor obtained by using the same method as in FIG. 1.
There are adjacently formed a p-well 24 and n-well 26 on an n-type or p-type semiconductor substrate 22. The p-well 24 and n-well 26 are electrically isolated from each other by a field oxide layer 28. A first source and drain 38, 39 of low concentration are separated by a channel region in the p-well 24. A second source and drain 40, 41 of high concentration are separated with a more distance than the distance between the first source and drain. Over the channel region is formed a gate insulated layer 30, on which is there formed a first gate 32. An oxide layer spacer 36 of a first width is formed on both side walls of the gate 32.
On the other hand, a first source and drain 42, 43 are separated by a channel region in the n-well 26. A second source and drain 44, 45 of high concentration respectively cover the first source and drain 42, 43. Over the channel region is formed a gate insulated layer 30, on which is there formed a second gate 34. An oxide layer spacer 36 of the first width is formed on both side walls of the gate 34.
However, in this PMOS transistor formed in the n-well 26 as shown in FIG. 2, if the distance of the p-type impurity exceeds the width of the spacer 36, the ion-implanted regions 44, 45 of high concentration cover the ion-implanted regions 42, 43 of low concentration.
Referring to FIG. 3 for illustrating another conventional semiconductor transistor, the width of the spacer is increased considering the out-diffusion of the p-type impurity.
There are adjacently formed a p-well 44 and n-well 46 on an n-type or p-type semiconductor substrate 42. The p-well 44 and n-well 46 are electrically isolated from each other by a field oxide layer 48. A first source and drain 58, 59 of low concentration are separated by a channel region in the p-well 44. A second source and drain 60, 61 of high concentration are separated with a more distance than the distance between the first source and drain. Over the channel region is formed a gate insulated layer 50, on which is there formed a first gate 52. An oxide layer spacer 56 of a first width is formed on both side walls of the gate 52.
The width of the spacer 56 contacting with the gate insulated layer 50 is about 2500.ANG.. In this case, although a PMOS transistor with LDD structure is obtained by sufficiently increasing the width of the spacer 56 so as to compensate for the adverse excessive diffusion of the p-type impurity, the increased width of the spacer 56 increases the diffusion resistance between the source and drain of the NMOS transistor so as to result in decrease of the drain current.
Thus, the PMOS and NMOS transistor regions of the conventional semiconductor transistor may not have the desired LDD structure, because each of the regions is subjected to the ion-implantation after simultaneously forming the spacers of both regions.